A network of this type is the subject matter of commonly owned U.S. patent application Ser. No. 339,101, now U.S. Pat. No. 4,473,900, filed Jan. 13, 1982 by three of us (Piero Belforte, Mario Bondonno and Luciano Pilati) jointly with two others. As particularly described in that application, whose disclosure is incorporated by reference into our present application, the network comprises a set of integrated outer modular units, a set of integrated inner modular units and a set of integrated central modular units, the outer and inner modular units being referred to as "folded" since each of them incorporates two switching matrices pertaining to nonadjacent stages of the network. Thus, each outer modular unit includes a first-stage switching matrix with inputs connected to incoming PCM lines and a last-stage switching matrix with outputs connected to outgoing PCM lines; each inner modular unit includes a second-stage switching matrix with inputs connected to outputs of several first-stage matrices and a penultimate-stage switching matrix with outputs connected to inputs of several last-stage matrices. Each "unfolded" central modular unit includes at least one middle-stage switching matrix whose inputs are linked to outputs of several second-stage matrices and whose outputs are linked to inputs of several penultimate-stage matrices; with a network having an odd number of stages greater than five, at least one other set of "folded" modular units could be used to accommodate additional switching matrices inserted in the input and output connections of the middle-stage matrix. Each modular unit further includes ancillary circuitry connected to its input and output ends for checking the performance of the associated switching matrix or matrices. The operation of the switching matrices is controlled by a multiplicity of base-level microprocessors, one for each modular unit, each of which is responsive to routing instructions from a higher-level controller and is connected not only to the associated switching matrix or matrices but also to the ancillary circuitry of the unit for the detection of operational errors.
As further described in that pending application, the ancillary circuitry of each modular unit comprises an upstream sampler and a downstream sampler for each switching matrix thereof, each upstream sampler having inputs directly connected to those of the associated matrix while each downstream sampler has inputs at least indirectly connected to the outputs of its matrix. The two samplers thus connected across a matrix extract respective bit combinations which are fed, with the necessary relative delay compensating for transit time, to comparison means within the associated microprocessor for the detection of possible disparities therebetween.
In order to facilitate detection of transmission errors not only in the switching matrices themselves but also in their interstage connections, the ancillary circuitry of at least the modular units following those of the first network stage is described as further comprising transceivers connected to the inputs of switching matrices of subsequent stages for feeding back bit combinations, identical with those extracted by the associated upstream samplers, to downstream samplers of preceding stages. More particularly, an output transceiver immediately downstream of each preceding switching matrix and an input transceiver immediately upstream of each subsequent switching matrix are integrated with their associated matrices in the respective modular units. In a modified structure each modular unit includes one or two input/output transceivers interconnected by two-way links to establish signal paths through all the stages of the network, each unit additionally having one or two feedback transceivers interconnected by bidirectional links to establish testing connections independent of the aforementioned signal paths.
The network of this pending application, however, is designed for centralized control by the exchange equipment and not for a distributed-control telephone exchange toward which current technology is evolving. A modular network structure suitable for interfacing with control means distributed on the network periphery is described in U.S. Pat. No. 4,201,890 in the names of Alan J. Lawrence et al. The latter network comprises several stages consisting of multiport switching elements whose 16 ports are integrated components each designed to handle 32 16-bit channels of a single nonstandard bidirectional PCM group. Each switching element is capable of identifying a free output channel through wired logic circuitry at each port. All other routing orders are provided stage by stage by the peripheral control means, using the same channel on which the conversation is to be routed.
The flexibility of utilization of a switching element in this system is limited by the presence of wired-logic routing circuits. Moreover, the routing procedures require the use of 16-bit messages which makes the system incompatible with the standard PCM technology and thus necessitates the use of special components which cannot be used in other parts of the telephone exchange or in combination with standard PCM channels; this requires the provision of interface circuits for signal-format conversion. Incompatibility with standard PCM systems is accentuated by the fact that the same channel subsequently used for speech is first utilized for signaling, making it necessary to complement transmitted messages with information indicating whether it pertains to speech or signaling. As routing control is left largely to the telephone exchange itself, the equipment of that exchange is burdened with the task of commanding the establishment of a connection by each individual switching element stage by stage. Finally, network diagnosis is not decentralized down to the level of the individual switching element and thus devolves entirely upon the supervisory units located at the network periphery.
Another example of a network for distributed-control telephone exchanges is described in a paper titled "Time-division distributed switching system" by Minoru Akiyama et al, presented at the International Switching Symposium of 21-25 Sept. 1981 in Montreal, Canada. This network consists of temporal switching stages controlled by microprocessors and of spatial switching stages with interstage connections implemented by 10-bit parallel PCM groups; it is capable of routing PCM channels autonomously with a step-by-step procedure on the basis of commands from control units distributed on its periphery. Routing orders again use the same channel that is subsequently utilized for speech; thus, the two additional bits serve to indicate whether the message pertains to signaling or speech. This type of structure requires two different kinds of switching elements for time and space switching; any expansion demands that interstage links be rearranged through a different configuration of spatial stages. The temporal switching element does not operate on standard serial PCM groups; here, too, interface circuits must convert such standard PCM groups--arriving from subscribers and from trunks--to the format required within the switching network. The use of 10-bit parallel PCM groups makes the connections between network switching elements cumbersome; switching capacity in terms of PCM channels handled by the basic module is limited. Also, as in the system of Lawrence et al, circuit diagnosis is not decentralized down to the individual basic-module level and thus devolves entirely upon the peripheral supervisory units.